Hello world, this article was for an old uni assignment. I wouldn’t know anything about this anymore!

**1. Circuit Function**

## 1.1. Brief

This 8 function 4 bit ALU was created by combining four 1 bit ALUs, each with the following components and functionality-

- XOR
- X = A XOR B

- AND
- X = A AND B

- OR
- X = A OR B

- Full Adder with Subtraction – Doubles as an Adder and Subtractor
- X = A + B
- X = A – B

- 4 Input Multiplexor – Provides shifting left, right and thru capabilities
- X = A Shifted left by 1 bit
- X= A Shifted right by 1 bit
- X = A

The above components are located in a Logic Unit as seen in section 2.8. The Logic Unit is part of the 1 bit ALU. The logic unit’s output is selected via an 8 input multiplexor as shown in section 2.9. This allows the selection of a particular function based on 3 bits. The design of the Shifter that is inside the Logic Unit, is more of a passive design as Pin A of the Logic Unit is only coupled to Pin T of the 4 input multiplexor. The brunt of the Shifter functionality lies in the wiring of the 4 ALUs to make a 4 bit ALU as seen in section 1.2 below. The following sections show the functionality of each component of the 8 function 4 bit ALU below.

## 1.2. 8 Function 4 bit ALU

# 2. Circuit Components

## 2.1. Full Adder

### 2.1.1. Circuit Diagram

Full_Adder.dwm | Full_Adder.dwt |

### 2.1.2. Truth Table

## 2.2. Full Adder with Subtraction

### 2.2.1. Circuit Diagram

Full_Adder_With_Subtraction.dwm | Full_Adder_With_Subtraction.dwt |

### 2.2.2. Truth Table

This circuit utilises the Full Adder component shown in section 2.1.1. When S is turned off (set to 0), this circuit becomes the full adder shown in section 2.1.1. To avoid duplication, the truth table below will only show values when S is turned on (set to 1).

## 2.3. 2 to 4 Decoder

### 2.3.1. Circuit Diagram

Decoder_2_4.dwm | Decoder_2_4.dwt |

### 2.3.2. Truth Table

The methodology for creating a 2 to 4 decoder was derived from http://www.cs.uiuc.edu/class/sp08/cs231/lectures/07-Decoders.ppt , accessed 22/04/2008. Although the schematic diagram was not shown in that source, I managed to implement the functionality of turning on and off this circuit via a pin called EN. This aids in the creation of a 3 to 8 decoder shown in section 2.4. The below truth table shows values when EN is turned on (set to 1). If EN is turned off, this circuit spits out no outputs.

## 2.4. 3 to 8 Decoder

### 2.4.1. Circuit Diagram

Decoder_3_8.dwm | Decoder_3_8.dwt |

### 2.4.2. Truth Table

The methodology for creating a 2 to 4 decoder was derived from http://www.cs.uiuc.edu/class/sp08/cs231/lectures/07-Decoders.ppt , accessed 22/04/2008. By having a 2 to 4 decoder that can be switched on and off via pin EN, we can couple 2 of these circuits to make a 3 to 8 decoder. Below is the truth table for this circuit.

## 2.5. 4 Input Selector

### 2.5.1. Circuit Diagram

Selector_4.dwm | Selector_4.dwt |

### 2.5.2. Truth Table

To list all possible inputs for the above circuit, a very large table would have to be produced, one with 256 lines. Therefore I have decided to simplify the table and provide more meaning. The truth table below shows that if A is on and if S1 is on, X will be on too. This pattern continues for each letter input. The alphanumeric input (the selector), passes the value of its corresponding input to X. eg. To pass the value of C, you must turn on S3, that way X will be what ever C is. If the value of C is 0, and S3 is turned on, the value of C will still be passed to X, in which X will be 0.

## 2.6. 8 Input Selector

### 2.6.1. Circuit Diagram

Selector_8.dwm | Selector_8.dwt |

### 2.6.2. Truth Table

To list all possible inputs for the above circuit, a very large table would have to be produced. Therefore I have decided to simplify the table and provide more meaning. This circuit works exactly like the one in section 2.5.1. The only difference with this one is that this selector has 8 Inputs. Like the one in section 2.5.1, the truth table below shows that the Selector (S1- S8) allows the value of the inputs (A- H) to be passed to X.

## 2.7. Multiplexor (3 to 8 Decoder & 8 Input Selector)

### 2.7.1. Circuit Diagram

Multiplexor_3_8_Dec_8_Sel.dwm | Multiplexor_3_8_Dec_8_Sel.dwt |

### 2.7.2. Truth Table

To list all possible inputs for the above circuit, a very large table would have to be produced. Therefore I have decided to simplify the table and provide more meaning. This Multiplexor allows us to input a 3 bit binary to use as a selector of 8 possible inputs (A – H)

## 2.8. Logic Unit (Logical AND/OR/XOR, Full Adder with Subtraction, Shifter)

### 2.8.1. Circuit Diagram

Logic_Unit_8_Functions.dwm | Logic_Unit_8_Functions.dwt |

### 2.8.2. Truth Table

To list all possible inputs for the above circuit, a very large table would have to be produced. Therefore I have decided to simplify the table and provide more meaning. The truth table below was constructed on the basis that there are five components which altogether make up 8 functions. All five components are wired in parallel. The light green sections below show all possible inputs and outputs for each XOR, AND and OR component. The cyan sections show all possible inputs and outputs for the Full Adder in Subtraction mode (**Sub **set to 1), while the pale blue sections show all possible inputs and outputs for the Full Adder in Addition mode (**Sub** set 0). The cyan and pale blue sections are a direct reflection of sections 2.1 and 2.2. The purple sections show all possible inputs and outputs for the 4 input multiplexor. When this component is wired into a 4 bit ALU it becomes a functional 4 bit shifter as discussed in sections 1.1 and seen in section 1.2. The 4 input multiplexor shown 2.8.1 has an EN pin wired to a Vcc-, this just mean that power is being sent to that pin (ie. Set EN to 1), resulting in the 2 to 4 decoder inside it to be turned on.

## 2.9. 1 Bit ALU (Logic Unit and Multiplexor)

### 2.9.1. Circuit Diagram

ALU_1bit_8_Function.dwm |

ALU_1bit_8_Function.dwt |

### 2.9.2. Truth Table

To list all possible inputs for circuit diagram 2.9.1, a very large table would have to be produced. Therefore I have decided to simplify the table and provide more meaning. This circuit utilises the logic unit and passes its value to X via the 8 input multiplexor. The 8 inputs of the multiplexor are selected depending on the value of S1 to S3 pins. See section 2.8.1 for the logic unit’s truth tables. The light green sections below shows all possible inputs and outputs when XOR, AND and OR functions are selected. The cyan sections show all possible inputs and outputs for the Full Adder’s addition function. The pale blue sections show all possible inputs and outputs for the Full Adder’s subtraction function. The purple sections show all possible inputs for when X becomes 1 and some possible inputs for when X become 0. The purple section is just a multiplexor in which it passes the value of A, L or R to X, depending on the value for S1, S2 and S3.

*Random*

Posted on December 26, 20110